The continuing trend of scaling down integrated circuits has forced the semiconductor industry to consider new techniques for fabricating precise components at sub-micron levels. Along with the need for smaller components, there has been a growing demand for devices requiring less power consumption. In the manufacture of transistors, these trends have led the industry to refine approaches to achieve thinner cell dielectric and gate oxide layers.
In dynamic semiconductor memory storage devices it is essential that storage node capacitor cell plates be large enough to retain an adequate charge (or capacitance) in spite of parasitic capacitance and noise that may be present during circuit operation. As is the case for most semiconductor integrated circuitry, circuit density is continuing to increase at a fairly constant rate. The issue of maintaining storage node capacitance is particularly important as the density of dynamic random access memory (DRAM) arrays continues to increase for future generations of memory devices. The ability to densely pack storage cells while maintaining required capacitance levels is a crucial requirement of semiconductor manufacturing technologies if future generations of expanded memory array devices are to be successfully manufactured.
As disclosed in U.S. Pat. No. 5,418,180, and U.S. Pat. No. 5,407,534, Hemi-Spherical Grain (HSG) silicon enhances storage capacitance when used to form the storage node electrode without increasing the area required for the cell or the storage electrode height.
A disadvantage of using HSG to form a capacitor structure (such as a container type structure) in a deep sub-micron process (a process utilizing lines width of less than 0.25 microns) is that a small change in the processing conditions may result in the grains of the silicon to overgrow and form discontinuous islands. When the size of the container formation needs to be reduced to such a degree that only a thin film is feasible, the grain formation could quite possibly consume all of the silicon film and form completely isolated grains. Additionally, the space between containers needs to have enough margin to prevent shorts that can be caused by subsequent chemical cleaning. Furthermore, capacitor plate surface enhancement is a finction of grain size when HSG is used and a grain size of 700-800 angstroms has been found to provide sufficient surface enhancement. However, a 700-800 angstrom grain size will not fit into a 0.18 .mu.m or less container structured capacitor plate.
The present invention, develops a method to fabricate a capacitor structure for sub-micron fabrication processes. In particular, the present invention provides a capacitor fabrication solution for processes using a device geometry of 0.18 .mu.m or smaller.
U.S. Pat. No. 5,418,180 and U.S. Pat. No. 5,407,534, are hereby incorporated by reference as if set forth in their entirety.